In order to mitigate overheated interior of a vehicle parked in the hot summer sun and thereby to make the entering into the vehicle more comfortable, microcontroller managed module for automatic ventilation of vehicle interior is made. The module is implemented using a microcontroller as a central logical unit and a series of sensors which provide sufficient data to ensure functional, but also efficient, reliable and safe ventilation. The ventilation process is performed by opening vehicle windows slightly, which enables air to circulate. Microcontroller controls the position of the windows autonomously and independently of the driver's presence, following predefined algorithm that uses sensors data obtained from the vehicle's surroundings. Besides temperature, the most important factors to ensure quality implementation of ventilation are detected movements around the vehicle, the presence of precipitation and other. This paper shows the components, their purpose and capabilities, advantages and disadvantages, as well as potential implementations and upgrades. The test results give insight into utilization options of this module and its usefulness.
This contribution describes three procedures and the related software operations which are used to obtain the pulse-width modulation (PWM) signal for industrial use. The hardware platforms used to generate the signals are embedded systems, manufactured in recent years. Three types of microcontrollers based on their register architecture were used: 8-bit ATMEGA 328P, 16bit SAB80C167 and 32-bit PIC32MX320F128H. PWM is a preferred way for control in modern semiconductor devices. The very short rising and falling time ensure the minimum of switching transition time respectively of the switching losses. In this context, the paper will analyze comparatively a new structure, related on a classical reference structure, both the hardware and the software. At the end of the paper some conclusions might be drawn on the code length, system latency and the technical limitations of their usual or rated performance.
A PIC microcontroller based digital electronic system has been designed to monitor the fuel level and total amount of load on the freighter and generate scan report for the captain of the freighter. The system is designed for three different freighter load levels; no load, optimal load and over load. At initial level it remains in no load status, when load increases and still remain in optimal level then the system notify crews to initiate voyage. If the load increases to over load level then the system gives alarm and sends alert message to the main control tower for necessary initiative. The communication between the vessel and main control tower is done by GSM module to ensure long distance reliable communication. For amenity, freighter fuel level is monitored in both analogue and digital scale. The system is implemented by PIC midrange microcontroller based hardware and low cost GSM module which makes it more economic, reliable and efficient
Nowadays, the biomedical instrumentation holds a prominent position within medicine. Following this trend, the BPM (beat per minute) has become an important tool to elucidate about the functioning of the organism and wakeup for anomalies by monitoring the heartbeat in the human body. These devices are mostly used in hospitals and clinics but are gradually finding their way into domestic use. This paper demonstrates on an approach to design a cheap, accurate and reliable device which can easily measure the heart rate of a human body.
Malaysia has periodic problems with air quality reaching hazardous levels because of smoke haze. The heavy haze, described as a pall of smoke caused widespread health problems especially among the elderlies, the young and kids. Haze is an atmospheric phenomenon where dust, smoke and other dry particles obscure the clarity of the sky. This haze pollution has serious implications to health as well as for the whole environment. This paper described a mobile monitoring system developed to detect the level of haze particulates. Data collection was achieved with the use of gas sensor, and mobile alert implementation was developed with Global System Mobile (GSM) connection and Short Messaging System (SMS).
The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multi-standard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances.
The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.
In a modern system-on-chip design, hundreds of cores and intellectual properties can be integrated into a single chip. To be suitable for high-performance interconnects, designers increasingly adopt advanced interconnect protocols that support novel mechanisms of parallel accessing, including outstanding transactions and out-of-order completion of transactions. To implement those novel mechanisms, a master tags an ID to each transaction to decide in-order or out-of-order properties. However, these advanced protocols may lead to transaction deadlocks that do not occur in traditional protocols. To prevent the deadlock problem, current solutions stall suspicious transactions and in certain cases, many such stalls can incur serious performance penalty. In this brief, we propose a novel ID assignment mechanism that guarantees the issued transactions to be deadlock-free and results in significant reduction in the number of transaction stalls issued by masters. Our experimental results show encouraging performance improvements compared with previous works with little hardware and power overheads..
Advanced computing systems embed spintronic devices to improve the leakage performance of conventional CMOS systems. High speed, low power, and infinite endurance are important properties of magnetic tunnel junction (MTJ), a spintronic device, which assures its use in memories and logic circuits. This paper presents a PentaMTJ-based logic gate, which provides easy cascading, self-referencing, less voltage headroom problem in precharge sense amplifier and low area overhead contrary to existing MTJ-based gates. PentaMTJ is used here because it provides guaranteed disturbance free reading and increased tolerance to process variations along with compatibility with CMOS process. The logic gate is validated by simulation at the 45-nm technology node using a VerilogA model of the PentaMTJ.
A field-assisted spin-torque transfer magnetoresistive RAM (STT-MRAM) cache is presented for the use in high-performance energy-efficient microprocessors. Adding field assistance reduces the switching latency by a factor of 4. An array model is developed to evaluate the switching energy for different field currents and array sizes. Several STT-MRAM-based cells demonstrate a 55% energy reduction as compared with an SRAM cache subsystem. As compared with STT-MRAM caches with subbank buffering and differential writes, a field-assisted STT-MRAM cache improves the system performance by 28%, with a 6.7% increase in energy.
With the advancements in semiconductor technology, there has been an increased emphasis in low-power design techniques over the last few decades. Reversible computing has been proposed by several researchers as a possible alternative to address the energy dissipation problem. Several implementation alternatives for reversible logic circuits have also been explored in recent years, like adiabatic logic, nuclear magnetic resonance, optical computing, etc. Recently researchers have proposed implementations of various reversible logic circuits in the all-optical computing domain. Most of these works are based on semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI), which provides desirable features like low power, fast switching and ease of fabrication. In this paper we present an all-optical implementation of a digital multiplexer using MZI switches. Both non-reversible and reversible versions of multiplexer design are proposed, along with analytical evaluation of the design complexities both in terms of delay and resource requirements. The final optical net lists obtained have been compared against traditional reversible synthesis approaches, by using an available synthesis tool and then mapping the reversible gates to MZI switch based implementations. Some techniques for optimizing the final optical net lists have also been proposed. Synthesis results for some reversible benchmark circuits and the standard functions of three variables are also shown.
As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. In this brief, we propose a new adder that outperforms all state-of-the-art competitors and achieves the best area-delay tradeoff. The above advantages are obtained by using an overall area similar to the cheaper designs known in literature. The 64-bit version of the novel adder spans over 18.72 μ2 of active area and shows a delay of only nine clock cycles, that is just 36 clock phases.
The goal of static test compaction is to reduce the number or tests, or the lengths of test sequences, without reducing the fault coverage. Static test compaction that reduces the number of tests was formulated as a set covering problem in order to benefit from the heuristics that exist for solving this problem. This paper applies set covering concepts and heuristics to static test compaction that reduces the length of a functional test sequence. Although set covering is not applicable directly to a single test sequence, it provides a theoretical framework and justification for a particular set of heuristics. The procedure uses a parameter denoted by n to determine the computational effort for computing the sets that are used for making compaction decisions. With n=1, the procedure is equivalent to a static test compaction procedure that does not use set covering. Experimental results demonstrate that shorter test sequences are obtained for n>1 than for n=1. A variation of the static test compaction procedure that produces a monotonic decrease in test sequence length with n is also described.
In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance. This paper investigates four types of PPA's (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)). Additionally Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated. These adders are implemented in verilog Hardware Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 13.2 Design Suite. These designs are implemented in Xilinx Virtex 5 Field Programmable Gate Arrays (FPGA) and delays are measured using Agilent 1692A logic analyzer and all these adder's delay, power and area are investigated and compared finally.
Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra-dense low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Nevertheless, since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This paper proposes a new design approach oriented to the implementation of binary comparators in QCA. New formulations of basic logic equations required to perform the comparison function are proposed. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. With respect to existing counterparts, the comparators proposed here exhibit significantly higher speed and reduced overall area.
Backup paths are widely used in IP networks to protect IP links from failures. However, existing solutions such as the commonly used independent model and Shared Risk Link Group (SRLG) model do not accurately reflect the correlation between IP link failures, and thus may not choose reliable backup paths. We propose a cross-layer approach for minimizing routing disruption caused by IP link failures. We develop a probabilistically correlated failure (PCF) model to quantify the impact of IP link failure on the reliability of backup paths. With the PCF model, we propose an algorithm to choose multiple reliable backup paths to protect each IP link. When an IP link fails, its traffic is split onto multiple backup paths to ensure that the rerouted traffic load on each IP link does not exceed the usable bandwidth. We evaluate our approach using real ISP networks with both optical and IP layer topologies. Experimental results show that two backup paths are adequate for protecting a logical link. Compared with existing works, the backup paths selected by our approach are at least 18 percent more reliable and the routing disruption is reduced by at least 22 percent. Unlike prior works, the proposed approach prevents the rerouted traffic from interfering with normal traffic.
Multihop cellular networks (MCNs) have drawn tremendous attention due to its high throughput and extensive coverage. However, there are still three issues not well addressed. With the existence of relay stations (RSs), how to efficiently allocate frequency resource to relay links becomes a challenging design issue. For mobile stations (MSs) near the cell edge, cochannel interference (CCI) become severe, which significantly affects the network performance. Furthermore, the unbalanced user distribution will result in traffic congestion and inability to guarantee quality of service (QoS). To address these problems, we propose a quantitative study on adaptive resource allocation schemes by jointly considering interference coordination (IC) and load balancing (LB) in MCNs. In this paper, we focus on the downlink of OFDMA-based MCNs with time division duplex (TDD) mode, and analyze the characteristics of resource allocation according to IEEE 802.16j/m specification. We also design a novel frequency reuse scheme to mitigate interference and maintain high spectral efficiency, and provide practical LB-based handover mechanisms which can evenly distribute the traffic and guarantee users' QoS. Our study shows that our scheme not only meets the requirement on coverage, but also improves the throughput while accommodating more users in MCNs.
This paper studies network resource allocation between users that manage multiple connections, possibly through different routes, where each connection is subject to congestion control. We formulate a user-centric Network Utility Maximization problem that takes into account the aggregate rate a user obtains from all connections, and we propose decentralized means to achieve this fairness objective. In a first proposal, cooperative users control their number of active connections based on congestion prices from the transport layer to emulate suitable primal-dual dynamics in the aggregate rate; we show this control achieves asymptotic convergence to the optimal user-centric allocation. For the case of noncooperative users, we show that network stability and user-centric fairness can be enforced by a utility-based admission control implemented at the network edge. We also study stability and fairness issues when routing of incoming connections is enabled at the edge router. We obtain in this case a characterization of the stability region of loads that can be served with routing alone and a generalization of our admission control policy to ensure user-centric fairness when the stability condition is not met. The proposed algorithms are implemented at the packet level in ns2 and demonstrated through simulation.
We consider the delay of network coding compared to routing with retransmissions in packet erasure networks with probabilistic erasures. We investigate the sublinear term in the block delay required for unicasting n packets and show that there is an unbounded gap between network coding and routing. In particular, we show that delay benefit of network coding scales at least as √n. Our analysis of the delay function for the routing strategy involves a major technical challenge of computing the expectation of the maximum of two negative binomial random variables. Previous characterizations of this expectation are approximate; we derive an exact characterization and analyze its scaling behavior, which may be of independent interest. We also use a martingale bounded differences argument to show that the actual coding delay is concentrated around its expectation.
Recent years have witnessed an increased interest in recommender systems. Despite significant progress in this field, there still remain numerous avenues to explore. Indeed, this paper provides a study of exploiting online travel information for personalized travel package recommendation. A critical challenge along this line is to address the unique characteristics of travel data, which distinguish travel packages from traditional items for recommendation. To that end, in this paper, we first analyze the characteristics of the existing travel packages and develop a tourist-area-season topic (TAST) model. This TAST model can represent travel packages and tourists by different topic distributions, where the topic extraction is conditioned on both the tourists and the intrinsic features (i.e., locations, travel seasons) of the landscapes. Then, based on this topic model representation, we propose a cocktail approach to generate the lists for personalized travel package recommendation.
The delay-tolerant-network (DTN) model is becoming a viable communication alternative to the traditional infrastructural model for modern mobile consumer electronics equipped with short-range communication technologies such as Bluetooth, NFC, and Wi-Fi Direct. Proximity malware is a class of malware that exploits the opportunistic contacts and distributed nature of DTNs for propagation. Behavioral characterization of malware is an effective alternative to pattern matching in detecting malware, especially when dealing with polymorphic or obfuscated malware. In this paper, we first propose a general behavioral characterization of proximity malware which based on naive Bayesian model, which has been successfully applied in non-DTN settings such as filtering email spams and detecting botnets. We identify two unique challenges for extending Bayesian malware detection to DTNs ("insufficient evidence versus evidence collection risk" and "filtering false evidence sequentially and distributedly"), and propose a simple yet effective method, look ahead, to address the challenges.
The concentration of data traffic towards the sink in a wireless sensor network causes the nearby nodes to deplete their batteries quicker than other nodes, which leaves the sink stranded and disrupts the sensor data reporting. To mitigate this problem the usage of mobile sinks is proposed. Mobile sinks implicitly provide load-balancing and help achieving uniform energy-consumption across the network. However, the mechanisms to support the sink mobility (e.g., advertising the location of the mobile sink to the network) introduce an overhead in terms of energy consumption and packet delays. With these properties mobile sink routing constitutes an interesting research field with unique requirements. In this paper, we present a survey of the existing distributed mobile sink routing protocols.
Multicopy utility-based forwarding algorithms are popular in opportunistic mobile networks. They aim to gain high system throughput while keeping the cost low. However, most of them ignore the fairness issue on the successful delivery rate among users. In this paper, we analyze the fairness evaluation of the success rate distribution, and we propose a new fair packet-forwarding strategy based on packet priority. We formulate the opportunistic packet-forwarding process as a discrete-time Markov chain and deduce a stationary probability distribution vector. Instead of taking the hill-climbing heuristic on utility comparison, we introduce a lower utility tolerance mechanism for the decision-making process of each node, and we theoretically demonstrate that the proposed mechanism may be used to control the success rate of packet delivery by changing a simple parameter. In addition, we adopt a message-duplication restricting mechanism to adjust the number of replications based on packet priority.
We study the multicast capacity under a network model featuring both node's mobility and infrastructure support. Combinations between mobility and infrastructure, as well as multicast transmission and infrastructure, have already showed effective ways to increase multicast capacity. In this work, we jointly consider the impact of the above three factors on network capacity. We assume that m static base stations and n mobile users are placed in an ad hoc network. A general mobility model is adopted, such that each user moves within a bounded distance from its home-point with an arbitrary pattern. In addition, each mobile node serves as a source of multicast transmission, which results in a total number of n multicast transmissions.
While peer-to-peer networks are mainly used to locate distinctive resources across the Internet, new interesting deployment eventualities are rising. Particularly, some applications (e.g., VoIP) are proposing the creation of overlays for the localization of services based on equivalent servants (e.g., voice relays). This paper explores the doable overlay architectures which will be adopted to provide such services, showing how an unstructured resolution based on a scale-free overlay topology is a good choice to deploy in this context. Consequently, we tend to propose EQUATOR (EQUivalent servAnt locaTOR), an unstructured overlay implementing the higher than mentioned operating principles, based on an overlay construction algorithm that well approximates an ideal scale-free construction model. We have a tendency to present both analytical and simulation results that support our overlay topology selection and validate the proposed design.
Infrastructure as a Service (IaaS) cloud computing has revolutionized the method one thinks of acquiring resources by introducing a straightforward change: permitting users to lease computational resources from the cloud provider's datacenter for a brief time by deploying Virtual Machines (VMs) on these resources. This new model raises new challenges in the design and development of IaaS middleware. One of these challenges is the need to deploy a massive number (tons or maybe thousands) of VM instances simultaneously. Once the VM instances are deployed, another challenge is to simultaneously take a snapshot of the many images and transfer them to persistent storage to support management tasks, like suspend-resume and migration.
Cloud computing permits customers with limited computational resources to outsource massive-scale computational tasks to the cloud, where huge computational power can be easily utilised in an exceedingly pay-per-use manner. However, security is the most important concern that forestalls the wide adoption of computation outsourcing in the cloud, particularly when finish-user's confidential knowledge are processed and produced throughout the computation. Thus, secure outsourcing mechanisms are in great want to not only protect sensitive information by enabling computations with encrypted information, however conjointly defend customers from malicious behaviors by validating the computation result. Such a mechanism of general secure computation outsourcing was recently shown to be possible in theory, however to style mechanisms that are practically economical remains a terribly difficult drawback. Focusing on engineering computing and optimization tasks, this paper investigates secure outsourcing of widely applicable linear programming (LP) computations. In order to realize sensible potency, our mechanism design explicitly decomposes the LP computation outsourcing into public LP solvers running on the cloud and private LP parameters owned by the customer.
Business processes are increasingly distributed and open, creating them susceptible to failure. Monitoring is, therefore, an vital concern not only for the processes themselves however also for the services that comprise these processes. We tend to present a framework for multilevel monitoring of those service systems. It formalizes interaction protocols, policies, and commitments that account for normal and extended effects following the language-action perspective, and permits specification of goals and monitors at varied abstraction levels. We have a tendency to demonstrate how the framework can be implemented and evaluate it with multiple situations that include specifying and monitoring open-service policy commitments.
TIn this paper, a new configuration of a three-phase five-level multilevel voltage-source inverter is introduced. The proposed topology constitutes the conventional three-phase two-level bridge with three bidirectional switches. A multilevel dc link using fixed dc voltage supply and cascaded half-bridge is connected in such a way that the proposed inverter outputs the required output voltage levels. The fundamental frequency staircase modulation technique is easily used to generate the appropriate switching gate signals. For the purpose of increasing the number of voltage levels with fewer number of power electronic components, the structure of the proposed inverter is extended and different methods to determine the magnitudes of utilized dc voltage supplies are suggested. Moreover, the prototype of the suggested configuration is manufactured as the obtained simulation and hardware results ensured the feasibility of the configuration and the compatibility of the modulation technique is accurately noted.
In this paper, a novel configuration of a three-level neutral-point-clamped (NPC) inverter that can integrate solar photovoltaic (PV) with battery storage in a grid-connected system is proposed. The strength of the proposed topology lies in a novel, extended unbalance three-level vector modulation technique that can generate the correct ac voltage under unbalanced dc voltage conditions. This paper presents the design philosophy of the proposed configuration and the theoretical framework of the proposed modulation technique. A new control algorithm for the proposed system is also presented in order to control the power delivery between the solar PV, battery, and grid, which simultaneously provides maximum power point tracking (MPPT) operation for the solar PV. The effectiveness of the proposed methodology is investigated by the simulation of several scenarios, including battery charging and discharging with different levels of solar irradiation. The proposed methodology and topology is further validated using an experimental setup in the laboratory.
This paper presents a universal active filter for harmonic and reactive power compensation for single-phase systems applications. The proposed system is a combination of parallel and series active filters without transformer. It is suitable for applications where size and weight are critical factors. The model of the system is derived and it is shown that the circulating current observed in the proposed active filter is an important quantity that must be controlled. A complete control system, including pulse-width modulation (PWM) techniques, is developed. Comparisons between the structures are made from weighted total harmonic distortion (WTHD). The steady-state analysis is also presented in order to demonstrate the possibility to obtain an optimum voltage angle reducing the current amplitude of both series and parallel converters and, consequently, the total losses of the system. Simulated and experimental results validate the theoretical considerations.
Islanding detection is critical to safety and power quality as well as the control mode of grid-interface power converters. This paper addresses the islanding-detection methods on the basis of the grid synchronization instability mechanism. Although many modified phase-locked loop (PLL) methods have been proposed to achieve islanding detection, the PLL modeling and design are not clear in the existing literature and a cut-and-trail process is usually required during the design phase. This paper proposes a systematic PLL modeling and design approach to evaluate different frequency-based islanding-detection methods. Two different types of PLL-based islanding-detection solution are discussed, accounting for a majority of the existing methods. The first method is to modify the PLL to constantly move the stable equilibrium point.
An active power filter implemented with a four-leg voltage-source inverter using a predictive control scheme is presented. The use of a four-leg voltage-source inverter allows the compensation of current harmonic components, as well as unbalanced current generated by single-phase nonlinear loads. A detailed yet simple mathematical model of the active power filter, including the effect of the equivalent power system impedance, is derived and used to design the predictive control algorithm. The compensation performance of the proposed active power filter and the associated control scheme under steady state and transient operating conditions is demonstrated through simulations and experimental results.
Due to the wind speed variation, wind shear and tower shadow effects, grid connected wind turbines are the sources of power fluctuations which may produce flicker during continuous operation. This paper presents a model of an MW-level variable-speed wind turbine with a doubly fed induction generatorto investigate the flicker emission and mitigation issues. An individual pitch control (IPC) strategy is proposed to reduce the flicker emission at different wind speed conditions. The IPC scheme is proposed and the individual pitch controller is designed according to the generator active power and the azimuth angle of the wind turbine.
Voltage ratings for HVdc point-to-point connections are not standardized and tend to depend on the latest available cable technology. DC/DC conversion at HV is required for interconnection of such HVdc schemes as well as to interface dc wind farms. Modular multilevel voltage source converters (VSCs), such as the modular multilevel converter (MMC) or the alternate arm converter (AAC), have been shown to incur significantly lower switching losses than previous two- or three-level VSCs. This paper presents a dc/ac/dc system using a transformer coupling two modular multilevel VSCs. In such a system, the capacitors occupy a large fraction of the volume of the cells but a significant reduction in volume can be achieved by raising the ac frequency.
B. E (Computer Science)
B. E (Electronics and Communication)
B. E (Electrical and Electronics Eng.)
B. E (Information Technology)
B. E (Instrumentation Control and Eng.)
M. E (Computer Science)
M. E (Power Electronics)
M. E (Control System)
M. E (Software Engg)
M. E (Applied Electronics)
M. SC (IT , IT&M , CS&M, CS)
B.Sc. (IT , CS)